VM-USB VME controller with USB2 interface

The VM-USB is a VME master with high speed USB2 interface. Enhanced functionality is given by the programmable internal FPGA logic which provides a VME command sequencer with 4kByte stack and 28kByte data buffer. Combined with the 4 front panel I/O ports this allows VME operation and data acquisition/buffering without any PC or USB activity.

All VM-USB logic is controlled by the XILINX Spartan 3 family FPGA. Upon power-up the FPGA boots from a flash memory. The configuration flash memory can be reprogrammed via the USB port, allowing convenient updates of the firmware. Following an open platform approach the user can develop his own FPGA configuration.

Features

• low-cost VME master with high speed USB2 interface, auto-selecting USB2/USB1.
• Can act as a slot-one bus arbiter and/or interrupt handler.
• Responds to all 7 interrupt requests IRQ1-7, can generate any of the 7 interrupts.
• 2 NIM input and 2 NIM output ports with user-programmable functionality including trigger, counter, delay-gate-generator, pulser.
• 4 user-programmable diagnostic LED's
• Logical operations performed by a Spartan 3 series FPGA, XC3S400, the FPGA configures itself upon power-up from a selected sector of the flash memory, which stores up to four configuration files. The boot sector is selected by setting of a front-panel rotary selector. Any of the four sectors of the configuration flash memory can be reprogrammed (up to 10,000 times) via USB.
• VME sequencer: Internal FPGA can be programmed to operate as command sequencer with 4kByte command stack and 28kByte for data buffering (FIFO or dual-port RAM), stack is programmable via USB or VME.
• Up to 32 MByte/s readout D32 (buffered) and BLT via USB2.
• Open architecture, allowing the user to develop his own FPGA configuration.
• Microsoft Windows (32-bit) and Linux support, LabView VI's (version 7.1 and 8.0),

Read-out modes

• Single word transfer D16, D24, D32, block mode BLT
• Addressing modes A16, A24, A32
• Autonomous (intelligent) readout pursuant to user-programmed stack. May include conditional readout controlled by the content of a hit register. May include multiple, conditional command stacks, action triggered by either USB, VME or external signal
• Total block memory of 32-kBytes that can be divided between the data buffer (FIFO) with programmable level of transfer trigger and command stack in a way different from the default 28/4 split.