ECTF H.110 (CT Bus) General and technical information

Telecom Power Bus

The -Vbat and VbatRtn telecom power supply busses shall be qualified in all ways to source unearthed secondary hazardous voltages as defined by IEC 950 and harmonized derivative specifications. The ‑SELVbat and SELVbatRtn busses are not qualified for secondary hazardous voltage distribution. Voltage sourced on the SELVbat bus shall be within SELV limits. The ringing busses shall be qualified in all ways to source unearthed secondary hazardous voltages as defined by IEC 950 and harmonized derivative specifications.

The telecom voltages are supplied via a Universal Mate N-Lock connector located on the rear of the backplane.

Caution:

Once input power is connected, hazardous voltage may be present on the backplane.
Do not handle the backplane after connecting input power.

Power supply connections

Terminal bars with M4 screw-type terminals are available to connect the main operating voltages of +5 V, +3.3 V and GND.
The auxiliary voltages +12 V and –12 V are connected via M3 screwtype terminals.

Frame ground connection

There is a solid electrically conductive frame GND surface in the bus board-to-card rack mounting area. An M3 screw-type terminal is used to connect the frame ground. When an extended terminal bar is installed, frame GND can be connected to GND in a star-shaped low-resistance arrangement.

A capacitor next to the mounting holes in each slot is standard equipment. These capacitors provide HFcoupling of CHA-GND with LOGICGND. A 1 MΩ resistor discharges the capacitors and electrostatic currents.

The „FG” pins in the P4 connector are also connected to this connector.

Utility connector

The special signals to the power supply unit and external LEDs are routed to separate plug-in connectors on the backplanes. 10 or 14-pin connectors are used depending on the backplane type.

JTAG connector

A separate 6-pin connector for JTAG boundary scan is implemented on the backplane.
Faster, simpler system initialization and testing by means of the JTAG bus even in the completely mounted state are achieved by direct access via an additional connector on the backplane.

Termination

In keeping with the specification, the 8-slot backplanes come with onboard Schottky barrier diodes across from the system slot to guarantee optimal reliability and transfer characteristics.

Shelf enumeration switch

Switch S1 allows a the backplane to be assigned a unique address for use with other backplanes within a system.
Configure the switches at SGA0-SGA4 to set a unique address.

Switch Assignments S1

Geographical Addressing

The RS backplanes support geographic addressing; each slot is individually addressed to match its slot number. Refer to CompactPCI Specification version 2.0 R3.0 for additional information on slot addressing. Geographic addresses are available for the CPCI bus at connector J2/P2 and for the CT bus at connector J4/P4. The addressing is set at the factory using the jumpers described below and does not need to be changed by the user.

Pin Assignments - Geographical Address

Slot Assignments

The System to Logical Slot Signal Assignment tables (for Bus A and Bus B) show the system slot to logical slot relationships on the RS backplane and the Clock, Address, Request, and Grant signal assignments.

J3/P3 Connector Pin Assignments

Rows Z and F of the edge connectors on the backplane are connected to the GND layer. Rows A to E have no connections on the backplane and are therefore available to the user for REAR-PANEL I/O applications.

J4/P4 Connector Pin Assignments

J5/P5 Connector Pin Assignments

Rows A to E have no connections on the backplane and are therefore available to the user for REAR-PANEL I/O applications. Refer to Computer Telephony Specification PICMG 2.5 R1.0 for further information.

Pin Assignments J1/P1 and J2/P2 CompactPCI System Slot 64-bit Connector

Pin Assignments

Mating Connector and Pins (e. g.)