SMPbus 3 U Series 40

The SMPbus system is based on the 8080/8085/8088 processors. The SMPbus is a bus system with monomaster capability and a synchronous bus protocol. An 8-bit format in a 64 kByte address space is used for data transfer (16-bit addresses). The specification calls for a clock frequency of 8 MHz.

Connectors

Completely equipped with socket connectors to DIN 41612, type C, 96 pins. All socket connectors have 0.6 x 0.6 mm wire-wrap posts. For connection to another assembly, the first and last slots are equipped with gold-plated posts. The socket connectors are mounted solder-free using the press-fit technique with a flexible press-fit zone.

Power and sense connections

The +3.3 V, +5 V and ground operating voltages are supplied via double Faston tabs combined with M4 threads. Single Faston tabs are available for the ±12 V, ±15 V and Ubat (battery supply) supply voltages.

The arrangement of the supply modules on the backplane ensures optimal daughter board supply and trouble-free operation.
The backplane is fitted with single spade connectors for picking off the sensor voltages 3.3 VSENSE/0 VSENSE and 5 VSENSE/0 VSENSE.
Each of these is decoupled by means of a tantalum capacitor which reduces the oscillation tendency in the power supply unit’s control circuit.

Terminating resistors

The 42 terminating resistors (3.3 kΩ against +5 V) for the bus signal lines are arranged in 5 resistor networks and mounted solder-free in precision press-fit contacts.

Prepared for terminal bars

The bus has been prepared for installation of terminal bars for +5 V and GND. The voltage drop can be significantly reduced particularly with high current loading by installing terminal bars.

Prepared for blocking capacitors

Dynamic parasitic voltages in the power supply can be reduced by installing blocking capacitors. The blocking capacitors assigned to the sense connections reduce the oscillation tendency in the power supply unit’s control circuit.

The electrolyte or tantalum capacitors bridge the power supply unit’s adjustment time in the event of large load steps in the system. The ceramic/multilayer capacitors assigned to the terminating resistors reduce the noise when several signal lines are switched at the same time. Several mounting sockets are available in each case.

High reliability due to optimal transfer characteristics

The worst-case noise voltage margin for LS drivers in the low range is 300 mV.

With a max. 240 mV crosstalk voltage, the reliability of the Hartmann SMPbus is very high. Thanks to optimal layout design, reflections on the signal lines are minimal even though the specification prescribes high-impedance line termination.