SMP16bus 3 U Series 44

The SMP16bus system is an enhancement of the SMPbus system. The SMP16bus is a synchronous monomaster bus system with an 8/16-bit data width and 20-bit address bus. The SMP16bus can address a memory range of 1 MByte. The SMP16bus provides 64 kByte for direct input/output and 4 kByte for memory mapped input/output (MMIO). Depending on the assemblies used, 8 or 16-bit data transfer is possible. 8 cascadeable interrupt lines are integrated in the system.

Innovations of the SMP16bus system

• Extension of data bus from 8 to 16 bits
• Extension of I/O address range to 64 kByte
• In preparation for future developments, a +3.3 V voltage supply is implemented on the bus
• The raw bus transfer rate was increased to > 10 MByte/s
• Standardized special signal assignments
• Increased electromagnetic compatibility
• Compatibility with SMPbus, enabling future use of existing SMPbus components on the SMP16-bus

Performance features

• Uniform impedance of all signal lines:
  The line and layer structures guarantee uniform surge impedance for all signal lines.
• Optimal transfer characteristics:
  The SMP16bus boards are executed as multilayer boards, with the Hartmann-specific layout design guaranteeing optimal transfer characteristics. Impedance steps in the course of a signal line and reflections were reduced to an absolute minimum.

Connectors

The backplane is completely equipped with socket connectors to DIN 41612, type C, 96 pins. The socket connectors are executed using the solder-free press-fit technique. Additional wiring may be implemented or modules may be inserted on the gold-plated wrap pins with a length of approx. 10 mm on the back of the bus board.

Stacking of bus boards

The arrangement of the resistor networks on the backplane permit stacking of backplanes or connectors at 3 HP intervals (no slots are lost).

Noise-free power supply due to installation of capacitors

Needle-shaped transients in the power supply lines are suppressed by the area capacitors in the multilayer. Tantalum capacitors support the main power supply in the terminator area.

Reliable signal transmission through termination

In the standardversion (option A), only the pull-up resistors (3.3 kΩ against +5 V) are integrated on the bus board.
The option D is intended to further improve the signal line transfer characteristics. In addition to the pull-up resistors, an AC termination (R = 50 Ω in series with 47 pF) against ground is implemented here. Both sides are fitted with terminators in case of variant D.

Low reflection guarantees optimal settling behavior and defined logic switching operations.

EMC-compliant design

There is a solid electrically conductive chassis GND surface in the backplaneto-card rack mounting area.

This guarantees EMC-tight mounting of the bus board on the card rack. HF coupling of card rack and system ground is implemented by capacitors (10 nF, 200 V in each slot).

Static charges are discharged via a resistor (≥ 1 MΩ). A connection element (Faston 6.3 x 0.8 mm) is provided for the chassis ground connection. The outer bus board layers are executed as a GND or VCC area. This eliminates radiated noise from data traffic on the backplane.